Synopsys Design Compiler Tutorial 2021: From RTL to Synthesis
: This traditional mode uses statistical models to estimate interconnect delays based on gate fanout and design size. It is less accurate for sub-micron designs.
################################################################### # Synopsys Design Compiler Automation Script ################################################################### # 1. Setup paths and directories file mkdir reports file mkdir outputs # 2. Read Design analyze -format verilog my_alu.v control_unit.v top_module.v elaborate top_module current_design top_module # 3. Link and Check link check_design # 4. Apply Constraints create_clock -name sys_clk -period 10.0 [get_ports clk] set_clock_uncertainty 0.20 [get_clocks sys_clk] set_input_delay 2.5 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 2.5 -clock sys_clk [all_outputs] set_driving_cell -lib_cell BUFX4 [remove_from_collection [all_inputs] [get_ports clk]] set_load 0.2 [all_outputs] # 5. Compile compile_ultra -gate_clock # 6. Generate Reports report_design > reports/design_summary.rpt report_area -hierarchy > reports/area_summary.rpt report_timing -max_paths 5 > reports/timing_worst_paths.rpt report_constraint -all_violators > reports/violations.rpt # 7. Export Outputs change_names -rules verilog -hierarchy write -format verilog -hierarchy -output outputs/top_module_netlist.v write_sdc outputs/top_module.sdc echo "========================================" echo "SYNTHESIS FLOW COMPLETED SUCCESSFULLY!" echo "========================================" exit Use code with caution. Executing the Script via Command Line
Beginning Pass 1 Mapping ... Processing clock clk (period 10.00) Optimization completed Total mapping time: 0:00:12 *********************************************************************** Final Area: 12543.2 um^2 Final Worst Negative Slack (WNS): 0.12 ns Final Total Negative Slack (TNS): 0.00 ns *********************************************************************** synopsys design compiler tutorial 2021
You can read HDL files using either the read_verilog / read_vhdl commands or the analyze and elaborate commands. The analyze and elaborate method is highly recommended because it checks syntax before building the design architecture.
# Define the symbol library (for schematics in GUI) set symbol_library slow.sdb
In the dc_shell prompt:
Here are the critical variable definitions you will set in your setup file:
report_area -hierarchy
set_clock_transition -max 0.080 [get_clocks core_clk] Synopsys Design Compiler Tutorial 2021: From RTL to
# Check design for issues (e.g., unresolved references, floating ports) check_design
# Check if all constraints are met check_timing > $report_dir/check_timing.rpt # Look for "unconstrained endpoints" – these are dangerous!
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